The present invention relates to CDC (clock-domain-crossing) technique which enables checking of synchronization circuits in asynchronous transfer of clocks.
In Soc (System on chip), there exist signals crossing an enormous number of clock domains on a single chip. If CDC (clock-domain-crossing) check is insufficient, an operation failure due to introducing a glitch (spike voltage at the time of switching input data) or an accident due to pass-through current may occur. Therefore, CDC check becomes important. In CDC check, a clock signal is propagated through the register based on information indicating a synchronous or asynchronous relationship of the clock signal to detect a register transfer point where the clocks have an asynchronous relationship, and it is checked whether or not the circuit related to the transfer is the desired synchronization circuit. An error analysis is then performed based on the check result.
Additionally, in an asynchronous transfer, the meta-stable state of a latch circuit which occurs due to an asynchronous input signal is regarded as a dangerous zone surrounded by the setup time and the hold time which are based on the rise or fall of the clock defined in the latch circuit. If the setup time or the hold time exceeds a certain period, the output signal becomes unstable. The state, being referred to as “meta-stable”, causes malfunction of the system. In order to address the meta-stability, a circuit configuration is employed which is failure-free even if meta-stability occurs, (see, for example, patent document 1 (Japanese patent Laid-Open No. 7-311735)).
Furthermore, for a logic simulator taking into account the timing error that may occur in an asynchronous circuit, a technique is known which suppresses a large amount of pseudo errors occurring in timing check (see, for example, patent document 2 (Japanese Patent Laid-Open No. 2004-30186)). Here, with a terminal and a given time of a particular cell being specified in the timing error constraint specification information, the logic simulator overrides violation of the timing limitation tolerance value detected within a predefined time with regard to the terminal of the particular cell specified in the timing error constraint specification information so as not to output an error message.
According to the conventional CDC (clock-domain-crossing) check method, there may be a case in which as many as 1M errors are output when checking a Soc having, for example, about 10M gates. Reviewing such an enormous amount of errors, the inventor of the present application found that, in most cases there is no obstacle for asynchronous transfer in terms of chip specification, even if the circuit itself is violating circuit synchronism. If there is no obstacle for asynchronous transfer in terms of chip specification even if the circuit itself is violating circuit synchronism, such a case is referred to as a pseudo error. However, it is considered difficult to find real errors from the above-mentioned 1M errors, which requires a long time for error-analysis.
It is an object of the present invention to provide a technology which reduces pseudo errors.
The above and other objects as well as the new characteristics of the present invention will be clear from the descriptions and the attached drawings of the present specification.